This invention pertains to data processing systems employing virtual memory organizations, and more specifically to the organization and operation of cache tables in such systems.
The cost of memory hardware practically limits the amount of semiconductor memory that can be used in a processor system. However, users are demanding broader capabilities from their systems than can be practically and economically supported by a reasonable amount of semiconductor memory. In order to expand its memory capability, a system can be provided with a virtual memory using secondary storage devices, such as electromagnetic disks or tapes, as an adjunct to the semiconductor memory.
The requirement for efficient utilization of a virtual memory system has led to the development of virtual addressing in which a virtual address defining the map of the entire memory system is subject to address translation that converts the virtual address into a physical address corresponding to a location in the main memory.
As is known, a virtual memory organization is transparent to the system user who writes programs for a processing system as though all sectors of the virtual memory space are equally accessible. However, the operating program of a virtual memory processing system manipulates the virtual address supplied by the user to shift data between the main semiconductor memory and the secondary memory so that currently-accessed memory segments are stored into the main memory when needed, and returned to the secondary memory when not needed. Conventionally, this process involves translation of the virtual address to the physical address, with the physical address identifying main memory storage space wherein the currently-used memory segments are stored.
In order to increase the speed with which address translation takes place, a memory address cache is often used. The cache can comprise a table associating the most recently accessed virtual addresses and their translated physical addresses. Thus, when a virtual address is produced by the central processing unit (CPU) of the processing system, a memory management unit (MMU) will first attempt to match the virtual address with an entry in the cache table. If the produced virtual address is contained in the cache table, the address translation is complete and the main memory location can be immediately accessed.
The cache table is normally constructed as a lookup table whose contents are the most recently-used physical addresses, each of which is stored together with a plurality of status or control bits. As is known, the status or control bits can be used to monitor, among other things, the frequency with which a physical address is referenced and whether or not data at the referenced main memory location indicated by the physical address has been modified.
A cache memory can take any one of several well-known general forms such as directly-, associatively-, set associatively-, or sector-mapped. See Computer Architecture and Parallel Processing, K. Hwang Et Al, McGraw-Hill, 1984. These representative cache memory organizations all require a two-level cache structure: the first level contains the virtual-to-physical memory address translation, while the second confirms that the desired memory sector indicated by the physical memory is actually in the main memory storage. This requires two lookup table operations and two levels of circuitry to implement them.
A simplified cache address table would reduce the total number of lookup table operations and the amount of circuitry.
It is therefore the principal object of the present invention to provide a cache address table affording a simplified lookup operation.
It is a further object of the present invention to reduce the hardware requirements for such a cache address table.